Mar 4 2010
FME and Vectron International today announced they will be demonstrating Fujitsu's CHArge-Interleaved Sampler (CHAIS) ADC technology with the Batboard evaluation platform at the annual OFC/NFOEC in San Diego, March 23-25, 2010. The ADC reference clock will be driven by Vectron's VS-401 VCSO.
"Vectron's innovation and leadership in SAW oscillator technology allows us to meet the ever-increasing performance demands of the next generation networks operating at 100Gbit/s and beyond," said Ben Witham, product line manager, Vectron. "Fujitsu chose the VS-401 for this demonstration at OFC because it is uniquely suited to deliver the extremely high performance necessary for the company's ADC technology."
"We are pleased to be collaborating with Vectron International to demonstrate real-world ADC and VCSO performance at these frequencies," said Neil Amos, communications business unit director, FME. "Vectron's technology offering for ultra-low jitter reference clock sources is complementary to Fujitsu's CHAIS ADC program, both developments serving as key enablers for 100G coherent receiver designs."
FME's second generation 8-bit CHAIS ADC for 100Gbps coherent receiver designs supports data rates up to 63GSa/s. Based on the same ground-breaking ADC architecture as Fujitsu's 56GSa/s CHAIS ADC, the new design will again offer the ultra-fast sampling rates, wideband input, low noise and high resolution required for optical data transport at 100Gbps over long-haul and ultra long-haul links.
Implemented in 40nm CMOS technology, the 63GSa/s CHAIS ADC will surpass even the low power performance of the first generation and will support higher FEC overheads for longer reach. The fundamentals of the CHAIS architecture support scalability to even higher sampling rates for future transport data rates (400Gbps/1Tbps) and power dissipation that scales with smaller process feature size.
Fujitsu's 4-channel CMOS design allows for more efficient integration with coherent receiver digital cores, typically comprising tens of millions of logic gates and a multi-terabit data transfer rate across the interface between core and ADCs. The CHAIS ADC is complemented by high speed SerDes from Fujitsu supporting a range of protocols and data rates. In addition, Fujitsu's expertise in advanced package design, including excellent thermal management and noise isolation, provides the complete solution for a turnkey coherent receiver SoC design.
Designed primarily for 100G Optical Applications, Vectron's VS-401 VCSO operates at 1.747 GHz with a control voltage range of 0.5 to 4.5V. The key feature of this VCSO is its ultra low output jitter at only 8 fs-rms (12 kHz to 20 MHz), which is well below the 100G reference clock specification. Housed in 13x20mm SMD package, the VS-401 runs off of a single +5V supply and provides a sinusoidal output of +8 dBm typical. Initially frequencies being supported are centered around 1.747 GHz plus or minus 5% with plans to support a VCSO at 2 GHz by Q3-2010.
The VS-401 complements Vectron's full line of VCSOs which include single frequency and frequency-selectable products ranging from 125 MHz to 1200 MHz, in both 5x7mm and 9x14mm SMD packaging, LVPECL or LVDS differential outputs, +2.5 and +3.3V supply voltages, and output jitter from 500 fs-rms down to 150 fs-rms.