A research team led by Prof. Kei-May LAU of the Department of Electronic and Computer Engineering at Hong Kong University of Science and Technology (HKUST) has recently developed a novel semiconductor deposition scheme and demonstrated high-performance photodetectors (PDs) grown on silicon-on-insulators (SOI) for silicon photonics.
These III-V photodetectors are qualified candidates for high-speed data communications in silicon photonics. These results point to a practical solution for the monolithic integration of III-V active devices and Si-based passive devices on the SOI platform in the future.
The ever-growing communication traffic is pushing the conventional electronic interconnection to the limit. Silicon photonics is regarded as an enabling technology to solve this pressing issue with its high-speed and large bandwidth capability, as well as scalable and high-throughput manufacturing. High-performance PDs are crucial optical building blocks in silicon photonic integrated circuits (Si-PICs). In addition to characteristics such as high responsivity, low dark current, large bandwidth, operation over a wide wavelength band, efficient light coupling with Si waveguides and CMOS compatibility are also needed for the PDs.
III-V photodetectors have long been deployed in InP-based photonic integrated circuits (PICs) because of their superior device performance. Recently, interest on III-V PDs grown on Si started to flourish complementing the research on integrating III-V lasers on Si and the eventual goal of having high-performance III-V-photonics integrated on the Si-photonics platform. For the III-V PDs on Si realized by traditional blanket hetero-epitaxy method, the thick buffer layers used for defect reduction make it challenging for light coupling with Si-waveguides and reported 3 dB bandwidths of these PDs often fall in the range of sub-10GHz.
The HKUST team developed the lateral aspect ratio trapping (ART) method to grow III-V materials on SOI without the need of thick buffers. III-V PDs grown on SOI by this method feature an in-plane configuration with the Si-device layer, which allows easy integration of the PDs and Si-waveguides. The team designed and fabricated III-V PDs with a variety of dimensions on a monolithic InP/SOI platform, also developed by the team. The PDs feature a large 3 dB bandwidth exceeding 40 GHz, a high responsivity of 0.3 A/W at 1550 nm and 0.8 A/W at 1310 nm, a wide operation wavelength span over 400 nm, and a low dark current of 0.55 nA. The photocurrents is adjustable for various applications by varying the length of the PDs. Design of interfacing these PDs with Si-waveguides can be flexible and simple.
For the first time, the team demonstrates III-V photodetectors grown on the monolithic InP/SOI platform (paper to appear in Light: Science and Application) to fulfill the stringent criteria for PDs in silicon photonics. "This was made possible by our latest development of a monolithic InP/SOI platform with both sub-micron InP bars and large-dimension InP membranes. Our team's combined expertise and insights into both device physics and growth mechanisms allow us to accomplish the challenging task of cross-correlated analysis of epitaxial growth, material characteristics and device performance," says Prof. Lau.
This is a collaborative work with a research team led by Prof. Hon-Ki TSANG of Department of Electronic Engineering at Chinese University of Hong Kong (CUHK).
The device fabrication technology in the work was developed at HKUST's Nanosystem Fabrication Facility (NFF) on Clear Water Bay campus. The work is supported by Research Grants Council of Hong Kong and Innovation Technology Fund of Hong Kong. This work has recently been published in Optica.