Feb 23 2008
Infinera will unveil its vision of the future of photonic integration for telecom networks at next week’s OFC/NFOEC 2008, the annual trade show and conference for the optical networking industry. The vision centers on capacity per chip as the key metric for enabling the efficient scaling of optical transport networks and maximizing total fiber capacity. Infinera envisages steady growth in the number of devices integrated onto a chip, enabling the aggregate data rate per chip to double roughly every three years.
Infinera anticipates the next increment in commercially available photonic integrated circuits (PICs) to be PICs with capacity of 400 Gigabits/second (Gb/s) per chip. This next milestone in scaling capacity will be accomplished with PICs integrating ten wavelengths operating at 40Gb/s per wavelength, using Differential Quadrature Phase-Shift Keying (DQPSK) advanced modulation. Infinera is describing results of the successful lab demonstration of a 400 Gb/s DQPSK PIC in another news release published today, Infinera Demonstrates 40G Advanced Modulation on a PIC. Based on expected scaling in PIC capacity per chip, Infinera anticipates producing within ten years PICs with an aggregate capacity per chip of 4 Terabits/second, or forty times the capacity of today’s 100 Gb/s PICs .
Capacity per Chip the Key Metric for Capacity, Cost, and Simplicity
Ongoing growth in high-bandwidth services and Internet Protocol (IP) traffic is expected to drive the need for significant scaling of optical transport networks. Scaling of network capacity alone will not meet the needs of carriers; the scaling of the network requires the simultaneous and proportionate advancement of capacity, cost, power consumption, size, reliability and complexity.
For the past decade the industry has focused on data rate per wavelength as a key measure of progress to address these challenges. While the jump in data rate per wavelength from 2.5 Gb/s to 10 Gb/s led to a reduction in cost per gigabit-kilometer, the move from 10 Gb/s to 40 Gb/s utilizing phase modulation architectures addressed the question of spectral efficiency but has not adequately addressed issues of cost, power, reliability, and complexity associated with an increased number of optical components.
Infinera believes that the fundamental driver of network cost is the number of components in the network. Large-scale photonic integration is the only technology that can address the multiple challenges faced by carriers today. Increasing capacity per chip can enable carriers to scale their networks, while simultaneously reducing cost and network complexity. Capacity per chip is therefore the most relevant metric for future optical networks. Optical transmitter and receiver chips are the basic “building blocks” of network bandwidth. Increasing capacity per chip not only raises the data rate of the system, but, equally important, it enables the system to reduce cost, space consumption, power consumption, and complexity while improving the reliability of the system by reducing the number of components or packages within each line card and also reducing the number of line cards per system. Fewer line cards, or field replaceable units (FRUs), enables service providers to reduce installation and configuration tasks and eliminate failure points. Without continually increasing the capacity of the basic “building blocks” of bandwidth deployment, network operators would be forced into an inexorable increase in their operational workload and operating expenses as bandwidth grows.
Today’s state of the art in photonic integration is the Infinera PIC with a capacity per chip of 100 Gb/s integrated in the Infinera DTN Digital ROADM and Wavelength Division Multiplexing (WDM) platform. These PICs consolidate more than 60 optical components integrating ten wavelengths operating at 10 Gb/s per wavelength. After just over three years of shipping product, Infinera’s PIC-based systems account for some 13% of the multi-reach DWDM market (source: Ovum RHK).
From this starting point, Infinera anticipates PIC capacity per chip to double every three years and plans to produce PICs capable of 400 Gb/s per chip in 2009. This growth path is expected to continue for at least ten years, leading to the commercialization of PICs with 4 Terabits/second per chip within ten years.
Increasing capacity per chip is made possible through the application of several important technologies, including; integration of more wavelengths on a single chip; use of advanced modulation techniques to code more data to each wavelength, and expanding the range of PIC operation across the full fiber spectrum. Photonic integration provides a technology platform that is well suited to the practical implementation of all these technologies.
For example, advanced modulation techniques such as DQPSK require the use of many optical functions per channel where simple modulation schemes often require just a single laser and modulator. By integrating all the optical functions for an advanced modulation scheme onto a single PIC, photonic integration dramatically simplifies the design and manufacture of an advanced modulation system, significantly reducing the number of discrete optical components and fiber couplings required.
Total Fiber Capacity up to 100 Terabits/second
Similarly, most optical transmission systems today operate in only a portion of the total optical fiber spectrum, typically the C-band, limited by the use of erbium-doped fiber amplifiers (EDFAs). By integrating optical functions such as amplification into PICs, Infinera expects photonic integration to enable optical transmission across the entire fiber spectrum, enabling scaling of total fiber capacity up to 100 Terabits/second. This will allow network operators to significantly scale total network capacity while avoiding or deferring costly fiber overbuilds.
The suitability of photonic integration technology to enable scaling in capacity per chip is underpinned by Infinera PICs’ track record for reliability in live commercial networks. Infinera PICs have now realized more than 50 million hours of operation in live networks without a single failure. Based on three years’ experience producing PICs for commercial deployment, Infinera believes PIC manufacture can follow a learning curve analogous to that seen in silicon chips, with density rising from dozens of devices per chip today to hundreds, and beyond, over time.
“If you scale the capacity of a network without making that system simpler to manufacture, simpler to deploy, and more reliable, you haven’t achieved anything,” said Infinera Chief Marketing and Strategy Officer Dave Welch. “Photonic integration is the only technology that can scale all the key parameters simultaneously.”
“Infinera’s PIC was a watershed in the evolution of optical networking, akin in importance to the invention of the erbium-doped fiber amplifier. Infinera’s PIC roadmap shows that we are indeed at the beginning of a new era in optical networking, the era of photonic integration,” said Sterling Perrin, Senior Analyst at Heavy Reading. Next month, Heavy Reading will publish a report titled “The Future of Photonic Integration for Optical Networks.”
Conclusion
Scaling capacity per chip will enable service providers to scale their networks and accommodate IP traffic growth, while minimizing the number of components and line cards at each node, reducing operational complexity, and increasing reliability.
“Our vision of a 400 Gb/s chip next year and a doubling of capacity per chip every three years is based on many years of research and development at Infinera and the knowledge we’ve gained after deploying thousands of PIC-based systems worldwide,” said Infinera CEO Jagdeep Singh. “We believe photonic integration is not only here to stay, but will before too long become the dominant and ubiquitous technology in optical networks.”